This invention relates in general to very large scale integrated circuits and more particularly to a VLSI circuit having a monolithically integrated test circuit therein.
In monolithically integrated circuits both the manufacturing costs per semiconducting crystal and the reliability are substantially determined by the number of outer terminals (pads). Since in digital circuits with an irregular substructure, the number of outer terminals only increases approximately with the square root from the number of contained gate circuits, and since, accordingly, both the costs and the failure rate per gate circuit decrease as complexity increases, the general trend of development is towards continuously more voluminous and, consequently, more complex integrated circuits. In English-language literature, such types of circuits are referred to as VLSI (very large scale integrated) circuits.
According to an article published on pages 65 and 66 of "Electronics", Dec. 8, 1977, one of the main problems of such large scale integrated circuits resides in testing the circuits following the manufacture. This not only applies to digital functional testing (in digital circuits), but also to parameter testing in preventing drift failures (in digital circuits and also in linear circuits). Moreover, it is mentioned in the aforementioned article that test patterns for the digital functional testing increase in their complexity exponentially as the number of gate circuits of the complex to be tested increases, unless additional test points are introduced. This leads to the fact that a considerable amount of the possible failures is not at all detected by the functional testing patterns. Therefore, the introduction of a large number of test points may substantially increase the failure-detection rate.
This, however, does not yet solve the problem of the aforementioned hidden failures. These failures (errors) may be caused in that circuit elements, such as gate or flip flop circuits, may be just on the verge of the functionability and, in the event of a small parametric deviation of a circuit element, might become completely unserviceable without this being able to be recognized owing to the non-linearities of the preceding and subsequently following circuit elements, in the course of measurements carried out at the outer terminals. Also failures of this kind can be recognized with the aid of suitable test points, the number of which, however, must be a considerable one for this purpose.
Considering that the test points which are to be provided additionally, are circuit points within the circuit of the VLSI circuit, these test points, in order to become electrically accessible at all, must be led at least to connecting pads provided for on the rim of the semiconducting crystal. From this fact there immediately results a substantial restriction of the number, because the marginal length of a semi-conducting crystal is limited, and in most cases these marginal areas are also already required for and occupied by the connection pads necessary for the operation. Moreover, the same consideration also applies to the outer terminals of the finished VLSI circuit is housed in a casing.